Because of high speed and low latency, SRAMs are often used as cache memories, control stores, buffer memories, instruction pipelines and data pipelines including input output interfaces and buffers for direct memory access (“DMA”) interfaces within microprocessors as well as for data storage used for communication interfaces, e.g., network adapter buffers. As the size and operating voltages of these devices decrease so does the size and operating voltage of the field effect transistors (FETs) in the cells of SRAM arrays. As the size and voltages decreases it has become increasingly more difficult to maintain specified operational margins of SRAMs. Accordingly, there exists a need in the art to maintain specified operational margins of SRAMs.